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IDT74GTLP16612 CMOS 18-BIT TTL/GTLP UNIVERSAL BUS TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
CMOS 18-BIT TTL/GTLP UNIVERSAL BUS TRANSCEIVER
FEATURES:
* * * * * * * * * * * * * * Bidirectional interface between GTLP and TTL logic levels Edge Rate Control Circuit reduces output noise VREF pin provides reference voltage for receiver threshold CMOS technology for low power dissipation Special PVT Compensation circuitry to provide consistent performance over variations of process, supply voltage, and temperature 5V tolerant inputs and outputs on A-Port Bus-Hold to eliminate the need for external pull-up resistors for unused inputs to A-Port Power up/down high-impedance TTL-compatible Driver and Control inputs High Output source/sink 32mA on A-Port pins Flow-through architecture optimizes system layout D-type latch and flip-flop architecture for data flow in clocked, transparent, or latched mode Open drain on GTLP to support wired OR connection Available in SSOP and TSSOP packages
IDT74GTLP16612 PRELIMINARY
DESCRIPTION:
The GTLP16612 is an 18-bit universal bus transceiver. It provides signal level translation, from TTL to GTLP, for applications requiring a highspeed interface between cards operating at TTL logic levels and backplanes operating at GTLP logic levels. GTLP provides reduced output swing (<1V), reduced input threshold levels, and output edge-rate control to minimize signal setting times. The GTLP16612 is a derivative of the Gunning Transceiver Logic (GTL) JEDEC standard JESD8-3 and incorporates internal edge-rate control, which is process, voltage, and temperature (PVT) compensated. GTLP output low voltage is less than 0.5V. The output high is 1.5V, and the receiver threshold is 1V.
FUNCTIONAL BLOCK DIAGRAM
OEAB 1
CEAB
56
CLKAB
55
LEAB
2
LEBA
28
CLKBA
30
CEBA
29
OEBA
27 ONE OF 18 CHANNELS CE 1D C1 CE 1D C1 CLK CLK
A1
3
GTLP
54
B1
TO 17 OTHER CHANNELS
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
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c 1999 Integrated Device Technology, Inc.
OCTOBER 1999
DSC-5477/1
IDT74GTLP16612 CMOS 18-BIT TTL/GTLP UNIVERSAL BUS TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
OEAB LEAB A1 GND A2 A3 VCC (3.3V) A4 A5 A6 GNDQ A7 A8 A9 A10 A11 A12 GND A13 A14 A15 VCC (3.3V) A16 A17 GND A18 OEBA LEBA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 CEAB CLKAB B1 GND B2 B3 VCCQ (5V) B4 B5 B6 GND B7 B8 B9 B10 B11 B12 GND B13 B14 B15 VREF B16 B17 GND B18 CLKBA CEBA
ABSOLUTE MAXIMUM RATINGS(1,2)
Symbol VCC VCCQ VI VO VO IOL IOH IOL IIK IOK IOK TSTG DC Input Voltage DC Output Voltage, 3-State DC Output Voltage, Active DC Output Sink Current into A-port DC Output Source Current from A-port DC Output Sink Current into B-port (in the LOW state) DC Input Diode Current VI < 0V DC Output Diode Current VO < 0V DC Output Diode Current VO > VCC Storage Temperature -50 -50 +50 -65 to +150 mA mA mA C -0.5 to +7 -0.5 to +7 -0.5 to VCC + 0.5 64 -64 80 V V V mA mA mA Rating Supply Voltage Max. -0.5 to +7 Unit V
NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Unused inputs without Bus-Hold must be held HIGH or LOW.
CAPACITANCE (TA = +25C, f = 1.0MHZ)
Symbol CIN CI/O CI/O Parameter(1) Control Pins A-Port B-Port Conditions VI = VCCQ or 0 VI = VCCQ or 0 VI = VCCQ or 0 Typ.(2) 8 9 6 Max. -- -- -- Unit pF pF pF
NOTES: 1. As applicable to the device type. 2. All typical values are at VCC = 3.3V and VCCQ = 5V.
PIN DESCRIPTION
Pin Names OEAB OEBA CEAB CEBA LEAB LEBA CLKAB CLKBA VREF A1 - A18 B1 - B18 Description(1) A-to-B Output Enable (Active LOW) B-to-A Output Enable (Active LOW) A-to-B Clock Enable (Active LOW) B-to-A Clock Enable (Active LOW) A-to-B Latch Enable (Transparent HIGH) B-to-A Latch Enable (Transparent HIGH) A-to-B Clock Pulse B-to-A Clock Pulse GTLP Input Reference Voltage A-to-B TTL Data Inputs or B-to-A 3-State Outputs B-to-A GTLP Data Inputs or A-to-B Open Drain Outputs
SSOP/ TSSOP TOP VIEW
NOTE: 1. A-Port pins have Bus-Hold. All other pins are standard input, output, or I/O.
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IDT74GTLP16612 CMOS 18-BIT TTL/GTLP UNIVERSAL BUS TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
RECOMMENDED OPERATING CONDITIONS(1)
Symbol VCC VCCQ VTT VI IOH IOL IOL TA Bus Termination Voltage Input Voltage on A-Port and Control Pins HIGH Level Output Current (A-Port) LOW Level Output Current (A-Port) LOW Level Output Current (B-Port) Operating Temperature Supply Voltage Rating Recommended 3.15 to 3.45 4.75 to 5.25 1.35 to 1.65 0 to 5.5 -32 +32 +34 -40 to +85 V V mA mA mA C Unit V
FUNCTIONAL DESCRIPTION:
The GTLP16612 combines a universal transceiver function with a TTL to GTLP translation. The A-Port and control pins operate at LVTTL or 5V TTL levels while the B-Port operates at GTLP levels. The transceiver logic includes D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clock mode.
NOTE: 1. Unused inputs without Bus-Hold must be held HIGH or LOW.
FUNCTION TABLE(1,2)
Inputs CEAB X L L X X L L H
NOTES: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care = LOW-to-HIGH Transition 2. A-to-B data flow is shown. B-to-A data flow is similar, but uses OEBA, LEBA, CLKBA, and CEBA. 3. Output level before the indicated steady-state input conditions were established, provided that CLKAB was HIGH before LEAB went LOW. 4. Output level before the indicated steady-state input conditions were established.
Outputs CLKAB X H L X X X Ax X X X L H L H X Bx Z B0(3) B0
(4)
Mode Latched storage of A data Transparent Clocked storage of A data Clock Inhibit
OEAB H L L L L L L L
LEAB X L L H H L L L
L H L H B0
(4)
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IDT74GTLP16612 CMOS 18-BIT TTL/GTLP UNIVERSAL BUS TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Industrial: TA = -40C to +85C, VREF = 1V, VCC = 3.3V 5%, VCCQ = 5V 5%
Symbol VIH VIL VREF VIK VOH A-Port Parameter B-Port All Other ports B-Port All Other ports -- -- -- -- -- -- -- VCC = 3.15V II = -18mA VCCQ = 4.75V VCC, VCCQ = Min to Max(2) VCC = 3.15V VCCQ = 4.75V VOH A-Port VCC, VCCQ = Min to Max(2) VCC = 3.15V VCCQ = 4.75V B-Port II Control Pins A-Port VCC = 3.15V VCCQ = 4.75V VCC, VCCQ = 0 or Max VCC = 3.45V VCCQ = 5.25V B-Port IOFF II (HOLD) IOZH IOZL ICCQ (VCCQ) A-Port A-Port A-Port B-Port A-Port B-Port A or B Ports VCC = 3.45V VCCQ = 5.25V VCC = VCCQ = 0 VCC = 3.15V VCCQ = 4.75V VCC = 3.45V VCCQ = 5.25V VCC = 3.45V VCCQ = 5.25V VCC = 3.45V VCCQ = 5.25V IO = 0 VI = VCCQ or GND ICC (VCC) A or B Ports VCC = 3.45V VCCQ = 5.25V IO = 0 VI = VCCQ or GND ICC (3) A-Port and Control Pins VCC = 3.45V VCCQ = 5.25V A or Control Inputs at VCC or GND
NOTES: 1. All typical values are at VCC = 3.3V, VCCQ = 5V, and TA = 25C. 2. For conditions shown as Max. or Min., use appropriate value specified under Recommended Operating Conditions. 3. ICC is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
Test Conditions
Min. VREF+ 0.1 2 0 -- -- -- VCC-0.2 2.4 2 -- -- -- -- -- -- -- -- -- -- 75 -20 -- -- -- -- -- -- -- -- -- -- --
Typ.(1) -- -- -- -- 1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 30 30 30 0 0 0 0
Max. VTT -- VREF- 0.1 0.8 -- -1.2 -- -- -- 0.2 0.5
Unit V V V V
IOH = -100A IOH = -8mA IOH = -32mA IOL = 100A IOL = 32mA IOL = 34mA VI = 5.5V or 0V VI = 5.5V VI = VCC VI = 0 VI = VCCQ VI = 0 VI or VO = 0 to 4.5V VI = 0.8V VI = 2V VO = 3.45 V VO = 1.5V VO = 0 VO = 0.65V Outputs HIGH Outputs LOW Outputs Disabled Outputs HIGH Outputs LOW Outputs Disabled One Input at 2.7V
V
V 0.65 10 20 1 -30 5 -5 100 -- -- 1 5 -20 -10 40 40 40 1 1 1 1 mA mA mA A A A A A
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IDT74GTLP16612 CMOS 18-BIT TTL/GTLP UNIVERSAL BUS TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS OVER OPERATING RANGE (1,2)
IDT74GTLP16612 Symbol fCLOCK tW tW tS tS tS tS tS tS tH tH tH tH tH tH tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tRISE tFALL tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ
NOTES: 1. See Test Circuits and Waveforms. TA = -40C to +85C. 2. Unless otherwise noted, VREF = 1V, CL = 30pF for B-Port, and CL = 50pF for A-Port. 3. Typical values are at VCC = 3.3V, VCCQ = 5V, and TA = 25C.
Parameter Max Clock Frequency Pulse Duration, LEAB or LEBA HIGH Pulse Duration, CLKAB or CLKBA HIGH or LOW Setup Time, Ax before CLKAB Setup Time, Bx before CLKBA Setup Time, Ax before LEAB Setup Time, Bx before LEBA Setup Time, CEAB before CLKAB Setup Time, CEBA beforeCLKBA Hold Time, Ax after CLKAB Hold Time, Bx after CLKBA Hold Time, Ax after LEAB Hold Time, Bx after LEBA Hold Time, CEAB after CLKAB Hold Time, CEBA afterCLKBA Ax to Bx LEAB to Bx CLKAB to Bx OEAB to Bx Transition Time, B outputs (20% to 80%) Bx to Ax LEBA to Ax CLKBA to Ax OEBA to Ax
Min. 175 3 3.2 0.5 3.1 1.3 3.7 0.4 1 1.5 0 0.5 0 1.5 1.7 1 1 1.8 1.5 1.8 1.5 1.6 1.3 -- 2 1.4 2.1 1.9 2.3 2.2 1.5 1.9
Typ.(3) -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 4.3 5 4.5 5.3 4.6 5.4 4.4 6.1 2.6 5.6 5 4.2 3.3 4.4 3.5 5 3.9
Max. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 6.5 8.2 6.7 8.6 6.7 8.7 6.2 9.8 -- 8.2 7.2 6.3 5 6.8 5.2 6.2 7.9
Unit MHz ns
ns
ns
ns ns ns ns ns ns ns ns
ns
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IDT74GTLP16612 CMOS 18-BIT TTL/GTLP UNIVERSAL BUS TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS
6V Open GND 500 FROM OUTPUT UNDER TEST 25 1.5V (GTLP)
FROM OUTPUT UNDER TEST CL = 50pF
500
S
30pF
NOTE: 1. CL includes probes and jig capacitance.
NOTE: 1. CL includes probes and jig capacitance. For B-Port outputs, CL = 30pF is used for worst case edge rate.
Test Circuit for A Outputs(1)
Test Circuit for B Outputs(1)
SWITCH POSITION
Test Open Drain Disable Low Enable Low Disable High Enable High All Other Tests Switch 6V GND Open
INPUT
1.5V tPLH tPHL 1V
3V 1.5V 0V VOH 1V VOL
OUTPUT
Voltage Waveforms Propagation Delay Times (A-Port to B-Port)
tW 3V INPUT Vm V Vm V 0V
Voltage Waveforms Pulse Duration (Vm = 1.5V for A-Port and 1V for B-Port)
NOTE: All input pulses have the following characteristics: frequency = 10 MHz, tR = tF = 2 ns, ZO = 50. The outputs are measured one at a time with one transition per measurement.
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IDT74GTLP16612 CMOS 18-BIT TTL/GTLP UNIVERSAL BUS TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS
3V TIM ING INPUT tSU Vm V 0V tH OUTPUT 3V DATA INPUT Vm V Vm V 0V 1.5V INPUT 1V tPLH tPHL
1.5V 1V 0V VOH 1.5V VOL
Voltage Waveforms Setup and Hold Times (Vm = 1.5V for A-Port and 1V for B-Port)
Voltage Waveforms Propagation Delay Times (B-Port to A-Port)
NOTE: All input pulses have the following characteristics: frequency = 10 MHz, tR = tF = 2 ns, ZO = 50. The outputs are measured one at a time with one transition per measurement.
OUTPUT CONTROL
3V 1.5V tPZL tPLZ 1.5V tPZH tPHZ VOH 1.5V VOH 0V
-
1.5V 0V 3V VOL VOL
+
OUTPUT W AVEFORM 1 (S AT 6V)
0.3V
OUTPUT W AVEFORM 2 (S AT GND)
0.3V
Voltage Waveforms Enable and Disable Times (A-Port)
NOTE: Waveform 1 is for an output with internal conditions such that the output is LOW except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is HIGH except when disabled by the output control. All input pulses have the following characteristics: frequency = 10 MHz, tR = tF = 2 ns, ZO = 50. The outputs are measured one at a time with one transition per measurement.
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IDT74GTLP16612 CMOS 18-BIT TTL/GTLP UNIVERSAL BUS TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
ORDERING INFORMATION
GTLP XX IDT XX Family Temp. Range XX XXX Device Type Package
PV PA 612 16
Shrink Small Outline Package Thin Shrink Small Outline Package 18-bit TTL/GTLP Universal Bus Transceiver Double-Density, High Drive, 32mA A Port +34mA B Port -40C to +85C
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